AMD lures high-ranking Itanium designer

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ISA becoming irrelevant

the encoding of an instruction set is really not all that interesting. yes, the RISC dogma of fixed-sized 32b instructions is very tidy, but it's certainly not optimal in the sense of maximizing code density.

as an outside observer, one of the major architectural themes of the 90's was that ISA became pretty much irrelevant, since everyone was translating ISA to broadly similar, RISC-ish internal formats. this is interesting because several of the original RISC motivations were specifically intended to avoid perceived bottlenecks at the fetch and decode stages. maybe some sort of technical breakthrough revolutionized decode, even for complicated encodings like x86.

in short, all the action is in portions of the CPU which are nearly encoding-independent nowadays. prefetching, prediction, scheduling, speculation, etc - all of which operate on internal micro-ops, not ISA instructions. for a chip architect, that's the interesting stuff, and there's plenty of opportunity to make AMD's chips zoom. the It2 has, in a way, been quite educational in showing which parts of an ISA are important, which are hard, which are irrelevant.

Posted by: markhahn   Posted on: 03/31/06 You are currently: a Guest | Members login | Terms of Use

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