Intel: x86 won't encroach on Itanium

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He he he ...

. . .
1) EPIC: radical departure from well understood / well accepted CISC or RISC technology. EPICs requ
ire very sophisticated compilers to leverage the inherent ILP. Applications written for the 32-bit
x86 need considerable effort to be ported to IA64. Operating Systems need even more effort.

``EPIC is the whole reason of Itanium damn it !!!
No EPIC = "another" Processor RISC based!!!! and not a breakthrough.''

What exactly do you mean? How this reply addresses to any of my points in my par. #1? You do not have to get so emotional: I didn't insult the ... honor of EPICs God forbids


2) Itanium has no specification for scalable systems architecture. Although SGI managed to glue 1000s of Itaniums together, it is using its own cache coherence protocols and inteconnect designs. If IA64 gets an 'upgrade' specification, SGIs design may have to be scrapped.

``This isn't CPU's problem damn it !!! CPU are intended to handle boolean logic. PERIOD.''

Thanks for the hint on boolean logic. However, cpus have evolved a ... little since the glorious 4004 era. CPUs have MANY more concerns than just handling boolean logic. It is how you PACK the transistors and how you interconnect them that matters right now. This determines clock speeds, noise levels, signal integrity, power consumption, etc. The problem of boolean logic is LOGICAL. Manufacturing an VLSI to implement it correctly and efficiently is a COMPLETELY different field of study. At the same time, connecting multiple processors into a COHERENT SMP system is MUCH MORE than bringing them physically close together.

One needs to design the ENTIRE MEMORY subsystem that goes with it. For large servers, one needs to design the cache coherence protocols and make sure that the mem. bandwidth requirements of the individual processors ARE DECENTLY met.

Why do you think Intel has BOTH Xeon (SMPs) and Pentium 4 (single processor systems)? Read up on these two and you will see the OBVIOUS system differences.

3) Itanium is a mem bandwidth hog. It demands very wide data buses to keep feeding it otherwise it
will be just stalling most of the time.

``You said "It demands very wide data buses"...
64 bit is 64 bitanywhere???? just for the sake of verify; is 2 times 32 bit... sure is "wider" than 32 bit x86 counterpart. You don't feed x86 CPU it also stall.''

I'll give you that 64-bit data buses are not so wide any more. However, 128 bytes wide L3 cache block is a tad big to feed and care for.


4) Itanium is not multithread friendly. Processors of this complexity need to execute multiple thre
ad contexts (SMT). Imagine a server receing 2,000-10,000 interrupts / sec (not uncommon in servers) which means that the processor will be just saving restoring context to service interrupts.

``Like in #1. Itanium handel interrupt differently. I recommend you to read about Itanium Prediction first then you could figure about multi whatever.''

So you mean that Branch Prediction, Predicated Execution and Speculative execution IMPROVES the performance of a large VLIW data path as that of Itanium's? Can you illustrate to us? All these fore mentioned 'gadgets' are nice for SINGLE instruction streams so they can exploit ILP. They work the opposite way in multiple thread enviornments WHICH ARE VERY COMMON in SERVERS.


5) Itanium consumes too much power and generates too much heat.

``Now I know why always desktop comes out first with new CPU and later laptop includes them!!!!''

The power consumption (and heating issues) is one of the most prevalent problems in Itanium, as openly admitted by Intel. Other processors (eg, Power5) consume much less power than Itanium-2.




``By allowing any dressed up monkey with internet access who wants to execute its constitutional right of free speech. Unfortunatelly not knowing the topic he is writting about. But who cares !!! it is my right to speak !!!''

Then don't get dressed up and do not speak.

Cheers,
-M

Posted by: michael-t   Posted on: 03/09/05 You are currently: a Guest | Members login | Terms of Use

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