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and when the quad-core core2 is out, their FSB is AGAIN
the bottleneck.

Intel does not know to design SMPs with more than 2 units. They always go with a fat, dumb and happy system controller chip which is unscalable and it routinely becomes their bottleneck. What they do is simply speeding up a bus (by improvements to signal transmission tech.) but they keep it multi-drop which almost immediately drops its max performance by a 30% for 2 and much more for > 2 units. The make also the FS Buses fatter (more lines).

They have never came up with a more intelligent design, even tehir own PCI-e technology is not leveraged to create P2P switched connections among parts. Tehy always go fo the simplest idea but then they quicckly hit the various tech. walls.

What is rediculous is the fact that after letting IA64 out to dry for theree years they came back with montecito which is simply 2 itanium-2 cores slapped together. Who is going to embark in the IA64 ship again?
Posted by: michael_t   Posted on: 07/21/06 You are currently: a Guest | Members login | Terms of Use

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This is a SUPER DUUHHHHHH !!!  michael_t | 07/20/06
super duh is right  yogeee | 07/20/06
I hope that IBM "siding" with AMD will further bolster AMD's  michael_t | 07/20/06
AMD better for MPP...  techboy_z | 07/21/06
and when the quad-core core2 is out, their FSB is AGAIN  michael_t | 07/21/06
More like  Wolfie2K3 | 07/21/06
Holdouts  Yagotta B. Kidding | 07/20/06
PR stunt to blunt Core2 Duo  Prognosticator | 07/21/06
Huh?  CattleProd | 07/21/06

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