IBM chip architect guns for gigahertz

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The perils of increasing frequencies: I can think of at least a dozen problems with increasing frequencies. I wonder if the IBM designers thought carefully about all of this before deciding on their clock frequencies?

- You need to reduce threshold voltage and increase supply voltage to gain the higher frequency. All this costs tremendous power. The total power consumption of the POWER6 is something that the IBM designers haven't divulged. That's probably because its a very high number; otherwise they'd be boasting about it, right?

- I wonder how much silicon the POWER6 team spent on cache structures. The memory wall would be a really big problem at such high frequencies.

- Wire delay is limited by the speed of light. Going to faster frequencies makes your wiring requirement much larger.

- Variability in sub 90nm generations is tremendous. The good thing the POWER6 team has done is not to increase the pipeline depth, but still, I expect significant problems with variability at such high frequencies. I've heard 6 GHz was the targetted frequency for the POWER6, but now they seem to be talking about 4-5GHz. Maybe the variability in critical paths stopped them from reaching 6 GHz.

- You'd have hotspots near the core regions at high frequencies. Cooling such hot spots is a big pain.

- High frequency effects such as inductance, crosstalk noise and di/dt noise would be tremendous.

- It makes life much easier for both design productivity as well as verification to have 4 lower frequency cores than to have 2 higher frequency cores.

- Clock power forms 40-50% of the total power in deep-submicron chips. The amount of clock power you spend for a high frequency chip would be significantly larger than for a lower frequency chip with more cores. Clock skew problems would also be minimized at lower frequency.

- With multicore chips, you can run each core at a different frequency and voltage to save power and gain performance when needed.

Despite all these advantages, multicores have one big disadvantage: software. I suppose the POWER6 architects went to high frequencies to maximise single thread performance. The POWER6 is meant for servers, so I guess it will encounter parallel code in some form. I wonder if the POWER6 designers will, in hindsight, rue their 5.5 GHz decision?; Posted by: deepaks_z Posted on: 03/01/06 You are currently: a Guest | Members login | Terms of Use