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INQ reported in September: Slow, late and underperforming

Intel's Montecito, Montvale beset by very hard times

Slow, late and underperforming


By Charlie Demerjian: Wednesday 28 September 2005, 09:37

MONTECITO AND MONTVALE are badly broken, late and overall rather anaemic. The reduced speed we told you about earlier were actually optimistic by 100MHz, so far, and it gets better. How much? Well, it is going to be really really late and de-featured. The current woeful state of affairs seems to be centred around power management, the vaunted Foxton looks like it is the root cause of the problems in a big big way, and it may well be the first bit on the chopping block.
But let's start with the good news, there really will be a 2.0GHz 24MB 800MHz FSB version. That is it. The bad news starts with when. As it stands right now, the launch is divided into two phases, and those are a bit fluid, and may change. I will give you the rosy outlook.

Phase one centres around one of two steppings, a C1 or Dx, depending on the state of C1 and whether it necessitates a Dx stepping. The current stepping C0 has taped out with 'sub-optimal validation', in 1337-speak, it means it was rushed out the door and buggy. Samples are expected to reach customers in about two months, and that is when the system level work can really begin.

If C1 ends up being the go-ahead version, unlikely because of the poor state of C0, then you will see a launch in late February. If they need a D-step, that could stretch out to Q2. This would mean the chips would be six months late.

Now, the real problem is what you will get when it comes out, or at least what phase one is. It seems that the chip has gone from 2.5GHz with a 24MB L3 cache, a 667FSB and Foxton to none of those. As late as this summer, it was going to be a 2.0/24/667 part. Now the launch will be an 1.6GHz part with nowhere near the cache and a 400FSB.

Ideas bandied about have all centred around losing the vaunted power management. It will be almost entirely gone except for the highest bin SKUs, and it may not make Phase 1 at all. The engineers looked at options of a 1.6GHz with a 1.8GHz Foxton boost, a 1.7 sans Foxton, or a 1.7/1.8. It seems yields would not support a 1.7/1.8 variant, so high end yields are thin at best, and the envelope is being pushed hard to get to the woeful numbers they are at. On the upside, if it gets delayed more, they could squeak a 1.8 variant out.

Phase 2 is when all the goodies come out. Intel is aiming for a hopeful 1.7 or 1.8 then, but the saving grace will be a 667FSB. Now, this will have to wait for an E Step, and right now it is looking like a Q4/06 launch. This might allow Foxton to be spread across the range, but considering the markets that the chips are being sold into, I kind of doubt they will add features to released chips later.

There was talk about a 533 or other intermediate FSB, but that was never a realistic option. It would have necessitated a full layer redesign, and Intel is not willing to do that. The order of the day is to pull as many resources off the project, not to add more.

What about Montvale though, the 3GHz 65nm wonder chip with revamped architecture which was summarily executed? The new variant is some of what Montecito was planned to be, and a little window dressing tossed in. The highest bin part is now scheduled as a 2.0GHz/24MB/800MHz FSB part with a 130W TDP. This means that Intel needed to to the classic bump the power to bump the speed - not a good sign. It is worse when you consider that was almost exactly the target for the 100W version, six plus quarters earlier.

There is also a MCM'd quad core part popping up, but it may still be shelved. This has some interesting possibilities, both positive and negative. The most obvious one is that it may lose a FSB step, but even if it doesn't, you will effectively halve the bandwidth per core. This makes it doubtful for HPC applications, they tend to be bandwidth bound to start with.

The point of the MCM parts is for business apps, a burgeoning marke, according to Intel Either way, since the 130W TDP is a hard cap, more from the vendors than Intel, it will probably mean a significant clock loss to achieve this goal. For some apps, it may make sense, but it will be far from being a panacea.

What do we have overall? Late, slow, underperforming chips with cracked technologies. IBM must be giggling like mad, because even if Power 5+ falls flat, there is little hope of the Mont- twins doing much other than vainly shooing for being in the same class as the current IBM offerings.

We believe SGI has an out strategy, and I think it will be a much better product when it arrives than the current IPF servers. It will appeal to a much wider audience, and in my view only really has upsides. HP on the other hand has its back to the wall. The other smaller vendors are faced with a late chip that hit the market with a whimper and underperforms their cutthroat competition.

The next version of the 'saviour chip', IE the wait till the next one, we really mean it this time chip, Tukwila is slipping like mad, and smart money has it not making 2007. Even if it does, where does that leave Montvale? 2007 is Power 6 time. I would say the competitive landscape has a vista of jagged and dangerous rocks, pitfalls and swamps. Intel and HP both of lengthy contractual obligations which means that these mariners on the ocean of enterprises have to live with loquacious albatrosses.

The last I heard, Intel's Poulson project was internally de-funded, but that is not a definite, and can be reversed. That could be undone. IPF's future looks pretty shaky. ?

Posted by: sharikou   Posted on: 10/24/05 You are currently: a Guest | Members login | Terms of Use

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