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- No flawed assumptions...
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I respectfully disagree with you assertion that VLIW and modern CPu design are 'flawed assumptions'. The issue facing Itanium is a combination of several things an not flawed architectural assumptions.
First, Moore's law as it is applied to the now ANCIENT X86 ISA coniues to add modern design approaches. X86 is effectively RISC and part VLIW when you consider micro-op techniques.
Secondly, Intel has ALWAYS manufactured Itanium processors ONE and sometimes TWO generations behind those of X86.
Third, compiler advances have not even been fully tapped to exploit perforamnce improvement. Everything is basically improved brute force in hardware because compilers are VERY hard. However, this stands to improve dramatically in the future. A simple re-ordering or rescheduling by a compiler can DRAMATICALLY impact performance. These are generally untapped capabilities that do NOT lend well to the crappy X86 ISA and limited resources.
I'd like to see the 'paper' you put out but I have been in front of enough smart people from Intel, IBM, (the old MIPS) , etc to be convinced that what ails Itanium is market dynamics of inertia, 'performance is good enough in Xeon', ...and NOT because the designis flawed. - Posted by: Prognosticator Posted on: 08/31/05 You are currently: a Guest | Members login | Terms of Use
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