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- Is almost as bad as folk knowledge
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Please cite a study that shows your contention. As a guy who wrote commercial compilers for almost all the major RISC chips when they came out I have seen no evidence of this claim.
In fact depending on the system and the software RISC versus CISC can vary all over the place. In particular, things like the size of the code versus the cache and memory can put RISC at a disadvantage.
Years ago, I did a study for a major PC manufactuerer on the potential performance on parallelism, from things like superpipeling, superscalar, and VLIW. One of the things that struck me was that research going back to the mid-60's was highly consistent on the performance benefits. Basically for common software (not special parallel cases) you find that there is improvement for up to 4 processing elements, after 4 improvement is rare.
After I did that study, I was talking to the head of Advanced R&D for the firm when Itanium first was being shown to the vendors. Intel was claiming great performance based on benchmarking Towers of Hanoi (the classic parallelism benchmark). I pointed out that they would never really get these numbers, and suggests they look at my paper again. I was later told I had predicted Itanium's performance curve very closely even though the paper was written years earlier.
Bottom line, is Intel based their design on flawed assumptions. There is no way to make this chip meet its hype. - Posted by: oldsysprog Posted on: 08/31/05 You are currently: a Guest | Members login | Terms of Use
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