Intel speeds dual-core Xeon debut

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At last Intel is forced into the

SMP arena. Now they cannot just keep boosting the clock of their dynosaurs. They need to address at last all the SMP issues including the cache coherence problem.

Just curious to see how they can keep the caches not startving for data, with a single bus system, since the FSB is already the bottleneck.

So, time to get to the drawing boards and start thinking of creative solutions. AMD has the hypertransport and it's a shame that Intel has not come up yet with a scalable design.....

-m

Posted by: michael_t   Posted on: 08/15/05 You are currently: a Guest | Members login | Terms of Use

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