Microsoft delays Windows Server update, 64-bit OS

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Credit where credit is due

I don't recall AMD ever claiming that Hypertransport would not use proven, existing bus architecture principles. It would be silly not to. That they kept the good ideas and fixed the rest is all the more reason for them to be praised, not reason to claim it's nothing new. A Boeing 777 keeps many of the principles introduced by Wilbur and Orville Wright intact. But you could hardly say that it's just an updated Wright Flyer.

As for Alpha vs Itanium:

Alpha EV6 architecture:
http://h18002.www1.hp.com/alphaserver/download/ev6chip.pdf

- RISC architecture
- 2x 80-register integer files, 1x 72-register fp file
- 64K L1 instruction cache, 64K L1 data cache
- 7 / 8 - stage pipeline

Intel IA-64 architecture:
http://www.hardwaresecrets.com/ia64.html

- EPIC / VLIW architecture (the exact OPPOSITE of RISC)
- 128 integer / 128 fp / 64 predict / 8 branch registers
- 16K L1 instruction / 16K L1 data / 96K L2 caches
- 10-stage pipeline


Dates:
Itanium introduced May 2001
http://www.intel.com/pressroom/archive/releases/20010529comp.htm

Alpha introduced Feb - Nov 2002 (*AFTER* Itanium)
http://research.microsoft.com/~gbell/Digital/timeline/64-bit.htm

Now, since Intel announced the Itanium *BEFORE* Digital had exposed the Alpha project, how was Alpha supposed to lead to Itanium? It makes much more sense to me that the goodies in Itanium came from its creators, Intel and HP, and their previous experience with Pentium and PA-RISC architectures. Of course, it goes in totally different direction with VLIW architecture anyway, but pieces of the puzzle are certainly shared.

Motorola and Digital have certainly contributed to the pool of microprocessor knowledge, but so have many others.

Posted by: TerryC_z   Posted on: 07/30/04 You are currently: a Guest | Members login | Terms of Use

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