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Data to bring ShadeTree into the light: ShadeTree wants some data on why some people think that the
RISC CPU is still better than a CISC CPU. Here are a couple of
sites to read about the differences in the two. The second one is
a bit more informative.

http://cse.stanford.edu/class/sophomore-college/projects-00/
risc/risccisc/

http://www.realworldtech.com/page.cfm?
ArticleID=RWT021300000000&p=6

The fact that Intel style CPUs have caught up to the abilities (in
most cases) of the RISC/ARM processors doesn't mean that they
are now better, just fast enough to blur the lines of difference.

As pointed out on the second site: "While the integer
performance gap between the best RISC and CISC processors has
closed over the last thirteen years, the deep and fundamental
differences between the two architecture design concepts have
not. The "RISC and CISC are converging" viewpoint is a
fundamentally flawed concept that goes back to the i486 launch
in 1992 and is rooted in the widespread ignorance of the
difference between instruction set architectures and details of
physical processor implementation. Modern out-of-order
execution x86 and RISC processors *do* have very similar
organization in their back end execution engines, both of may
which contain 40 or more physical renaming registers. While
RISC data paths are driven directly by RISC instructions, x86 data
paths are similarly driven by sequences of simple, shallowly
encoded microcode-like control words called micro-ops, or
provocatively, RISC-ops.
Even if the physical implementation advantages RISC designs
enjoy over CISC designs, like the x86, could be reduced to zero
(a prospect which is demonstrably remote), it doesn't change the
fact that the ISA, the programming model targeted by compilers,
is vastly different. The modern x86 processor might have 40
physical general purpose registers for renaming, but the
compiler can only target the 8 GPRs visible in the ISA. It doesn't
matter that the modern x86 processor has a back-end execution
engine that is controlled by RISC-like control words; these
micro-ops are inaccessible from the outside world and the
compiler cannot target them. The x86 compiler cannot perform
many of the standard RISC compiler optimization techniques
that strongly depend on large register sets, three address
instruction formats, and the absence of non-register based
dependencies between instructions.
This fundamental and inescapable nature of the difference
between RISC and CISC computer design is the driving force
behind both Intel's development of the 64-bit RISC-like IA-64
family of processors to eventually replace x86, and AMD's
decision to add a RISC-like large flat floating point register file
and three address floating point instructions to beef up the
performance of the 64-bit extended x86-64 ISA for its
upcoming K8 processor.

Both styles have their strengths and if those are used properly
then the end user needs to know little of the inner workings, it
just works.; Posted by: Mr_Dave Posted on: 09/29/05 You are currently: a Guest | Members login | Terms of Use